In semiconductor manufacturing technology, the critical dimension (CD) of a mask or wafer are becoming continually smaller for process technologies. It is important that the uniformity of the CD for various patterns (e.g., line width or line spacing), referred to as CD uniformity, remains at acceptable levels. However, CD variation may still have an adverse effect on subsequent processing. For example, an implantation process that forms various doped features such as lightly doped source/drain features of transistors may not be uniform across the semiconductor wafer due to CD variation of gate widths. Accordingly, performance characteristics of the transistors such as threshold voltage may fluctuate from die to die which can lead to poor device performance and low yield.